This invention relates generally to programmable logic block cell structures and in particular to an optimized programmable logic allocator in a very high-density complex programmable logic device (CPLD) that provides enhanced logic utilization and enhanced logic efficiency.
Programmable logic device (PLD) designers have consistently sought to maximize logic efficiency for a fixed amount of logic resources. One measure of logic efficiency in a programmable logic device is the number of product terms available per input/output (I/O) pin and the number of product terms at each node, usually a macrocell output line, that can be feedback to a programmable array in the PLD. Typically, in a programmable logic device, the product terms are not connected directly to an I/O pin but rather reach the I/O pin through a macrocell and perhaps other logic. Nevertheless, in each PLD, a specific number of product terms can be associated with each input/output pin. Similarly, a specific number of product terms can be associated with the output line of the macrocell or other logic.
Historically, low-density PLDs encompass monolithic block based structures in 20- to 28-pin packages with a density ranging from eight to sixteen macrocells. The architecture of a typical low-density PLD includes a programmable array logic (PAL) (PAL is a registered U.S. trademark of Advanced Micro Devices of Sunnyvale, Calif.), or a field programmable logic array (FPLA) with an integrated array of logic, I/O macrocells, and I/O pins.
Fundamentally, a simple PAL architecture incorporates a two-level logic array that has a programmable-AND plane, that consists of multiple product terms, and a fixed-OR plane. FPLA devices have both a programmable-AND plane and a programmable-OR plane. Typically, any logic function can be implemented in a low-density PAL device as long as the design requirements do not exceed the number of input signals, output signals, the logic product terms, and other logic functions, such as registers, clocks, polarity control etc., that are available in the PAL device.
The low-density PAL device is a simple structure and has the advantage of higher speed in comparison to a FPLA. In the low-density PAL device, a fixed and equal amount of logic, i.e., number of product terms, was associated with each output pin. Seven or eight product terms per each output pin was typical for first and second generation bipolar and CMOS PAL devices such as 16xx, 20xx, 16V8 and 20V8. One example of a low-density PAL device is shown in Birkner et al., U.S. Pat. No. 4,124,899 entitled xe2x80x9cProgrammable Array Logic Circuitxe2x80x9d and issued on Nov. 7, 1978, which is incorporated herein by reference in its entirety.
These low-density PAL devices had a fully committed structure which means that all of the internal elements and fixed logic allocation structure are closely coupled. The closely coupled structure, e.g., a PAL structure with a fixed product-term distribution, has several advantages including regularity or symmetry; a simple structure; a known amount of logic with each output pin; and ease of design changes.
While a PAL structure with a fixed product-term distribution had the above advantages, a fixed allocation of product terms had some major disadvantages. Since the number of product terms in the low-density PAL devices for each output pin was fixed and not steerable or sharable between adjacent output pins, the product terms associated with a particular output pin were wasted if that output pin was not utilized. Thus, the silicon efficiency was low.
Another major disadvantage of a fixed product-term distribution per output pin was that an optimal allocation of logic resources was not possible in most cases. Different logic applications seldom need the same and equal number of product terms for all output pins. There are many occasions when seven to eight product terms per output pin are not enough to handle complex logic functions, especially for complex state machines. Applications requiring only one more product-term than the fixed number of product terms for only one output pin cannot be implemented in a low-density PAL device.
Experience has shown that for a broad range of applications, eight product terms per output pin are on average more than enough. However, as for any average, eight product terms are insufficient in some cases. For example, FIG. 2 in Munoz et. al., xe2x80x9cAutomatic Partitioning of Programmable Logic devices,xe2x80x9d VLSI Systems Design Magazine, pp 74-78, October 1987, is a graph of product-term requirements for a relatively large sample of logic functions. This and other studies have shown that a large percentage of logic functions (on the order of 30 to 40%) require less than four product terms. However, a relatively significant xe2x80x9ctailxe2x80x9d exists where eight product terms are not enough.
One way to achieve increased product-term utilization over the fixed product-term distribution in low-density PAL devices is to provide a PLD with a fixed, variable product-term distribution per output pin. The concept behind the fixed, variable product-term distribution was to have a judicious allocation of logic resources and to allocate product terms in a variable but fixed distribution fashion such that some OR gates are driven by a few product terms, e.g., four or eight, and other OR gates are driven by a relatively large number of product terms, e.g., twelve or sixteen.
One of the first PAL devices to introduce a variable product-term distribution was sold by Advanced Micro Devices (AMD) of Sunnyvale, Calif. under Model No. PAL22V10. The number of product terms per I/O pin in the PAL22V10 architecture was 8, 10, 12, 14, 16, 16, 12, 14, 12, 10, and 8. This fixed, variable, static distribution of product terms enhanced the PAL device""s logic utilization by allowing use of the PAL device in a broader range of applications. Various PLDs that have incorporated the a fixed, variable, static distribution of product terms include PLDs sold by AMD under Model Nos. PALCE22V10 and PALCE29M16/29MA16. U.S. Pat. No. 4,717,912 issued to Harvey et. al., in January 1988, which is incorporated herein by reference in its entirety, illustrates a PLD with a fixed, variable product-term distribution.
While the fixed, variable distribution of product terms also results in a potentially better allocation of resources thereby enhancing product-term utilization over a comparable PLD with a fixed allocation of product terms, the fixed, variable distribution of product terms also results in a potentially inefficient silicon structure. Specifically, this product-term distribution increases the average number of product terms per output pin over the low-density PAL structures. The increase in the average number of product terms results in a bigger die size, potentially slower speed, and a greater likelihood of wasted resources.
The fixed, variable distribution of product terms restricts only a limited number of output macrocells and output pins to the largest amount of logic, and system designers have to pre-assign logic functions that require larger logic resources to only those particular output pins. Also, since the product-term distribution is fixed, output pins with a smaller number of product terms do not have access to unused product-term resources from other macrocells. This results in potential waste of internal resources. Extension of the fixed, variable product-term distribution to higher density devices with more output pins and macrocells would result in significantly larger, more expensive and slower devices.
The fixed, variable product-term distribution increases the complexity of the logic fitting software task because each user logic function must be examined and then, depending upon the demand for product-term resources, assigned to a specific output macrocell which has the minimum product terms needed to fulfill the required product-term demand. This software complexity becomes significantly worse for multiple interconnected programmable logic blocks that each have a fixed, variable product-term distribution.
The programmable logic devices disclosed in U.S. Pat. No. 5,015,884 entitled xe2x80x9cMultiple Array High Performance Programmable Logic Device Familyxe2x80x9d of Om P. Agrawal et al. issued on May 14, 1991, and in U.S. Pat. No. 5,225,719 entitled xe2x80x9cFamily of Multiple Segmented Programmable Logic Blocks Interconnected by a High Speed Centralized Switch Matrixxe2x80x9d of Om P. Agrawal et al. issued on Jul. 6, 1993, both of which are incorporated herein by reference in their entirety, eliminated the fixed connectivity of product terms to a macrocell and consequently an output pin. A programmable logic allocator 111 (FIG. 1) was inserted between a product-term array 110 and the logic that coupled the product terms to the I/O pins. In that PLD, each product-term cluster had four product terms, and the maximum number of product-term clusters steered to an I/O pin was three.
In FIG. 1, boxes L1 through L16 on the left-hand side of the figure, each of which contains the numeral xe2x80x9c4xe2x80x9d, represent the four product-term clusters in product-term array 110. Four product-term clusters were used because extensive studies of applications indicated that four to sixteen product terms per macrocell, preferably with D and T type flip-flops, allows addressing 90-95% of PAL replacement application needs. Also, it was found that any amount of fixed allocation of resources with output pins resulted in potential waste of resources.
On the right-hand side of FIG. 1 are sixteen boxes R1 through R16 which represent logic that couples the output signals of logic allocator 111 to the I/O pins. The number within boxes R1 to R16 is the maximum number of product terms that logic allocator 111 can route to a macrocell and consequently a particular I/O pin. Each line within logic allocator 111 represents a router element, and the numbers on a line within logic allocator 111 represent the product-term clusters, as numbered on the left-hand side of the figure, that can be steered to an I/O pin by that router element. Thus, in this PLD, an output terminal of the router element is programmably connectable to a maximum of three product-term clusters.
Logic allocator 111 provided programmable connectivity between product-term resources and macrocells, and so removed the limitation of fixed connectivity. No fixed amount of logic was associated with any macrocell, but some macrocells had the flexibility to receive up to twelve product terms of logic, when needed. Since the macrocells were coupled directly to I/O pins, each I/O pin had access to the same logic as the macrocell to which the I/O pin was coupled.
Logic allocator 111 was structured to achieve a balance between speed and logic flexibility. Logic allocator 111 allowed a product-term cluster to be steered to either two or three adjacent macrocells with no or minimal speed penalty. Also, symmetry was compromised for speed by not allowing complete wrap-around at the ends of logic allocator 111. Wrap-around capability introduces additional speed delay. Alternatively, additional product-term resources could have been used to simulate complete wrap-around. However, this results in a larger die size.
While logic allocator 111 permitted steering of a product-term cluster and hence improved logic flexibility, logic allocator ill did not allow product-term sharing. While the product-term clusters are available to multiple macrocells, a product-term cluster can be used by only one logic macrocell. Thus, product-term clusters are essentially stolen from adjacent logic macrocells. Once stolen, a product-term cluster was not available to other macrocells.
The operation of logic allocator 111 has implications in fitting a user logic design to the PLD. After a user has pre-placed some of the output pins and fixed the logic design, a subsequent change to the logic, that had once fitted nicely in the PLD, could potentially result in logic that no longer fit after the logic change. This can create a problem for board designers. This particular restriction may force a user to finish the board design before the board layout. This often can be a bottleneck for time-to-market considerations.
To illustrate the limitations of logic allocator 111, consider a PLD with a programmable logic block that includes eight macrocells R1 to R8, a logic allocator 111A, and a PAL array 110A with eight four product-term clusters C1 to C8. FIG. 2A illustrates the product-term clusters available to each router element in logic allocator 111. FIGS. 2B to 2J illustrate alternative configurations of the PLD upon programming logic allocator 11A. Specifically, FIGS. 2B to 2J illustrate connection of the specific product terms on the line representing the router element to the associated macrocell.
Logic allocator 111A (FIG. 2A) can steer a product-term to a maximum of any one of three adjacent macrocells but steering is not allowed to wrap-around at the ends of logic allocator 11A. As shown in FIG. 2B, each of macrocells R1 to R8 can have an average of four product terms without any problem.
If there is a need for increased flexibility, only certain combination of macrocells R1 to R8 and consequently output pins can have eight product terms, twelve product terms or sixteen product terms. It is not possible to provide a uniform eight product terms to each macrocell. If all thirty-two product terms are utilized and eight product terms are required, the closest that uniformity can be approached is by utilizing only every other macrocell as illustrated in FIG. 2C.
If it is necessary for two adjacent pins to have eight product terms and to utilize all thirty-two product terms, only certain macrocells can be utilized. FIGS. 2C to 2E illustrate possible combinations where two adjacent pins have eight product terms and all thirty-two product terms are utilized. It is possible to have three adjacent pins with eight product terms each only by using macrocells R3 to R5 (FIG. 2F). It is not possible to have four adjacent output pins with eight product terms each.
FIGS. 2G and 2I illustrate some possible configurations with twelve product terms. It is not possible to have two adjacent macrocells with twelve product terms.
To utilize all thirty-two product terms, and have sixteen product terms at the output pins, only output pins 2 and 6 (FIG. 2J) can be utilized because only these output pins can receive sixteen product terms. This is the only combination allowed. While the steering of product-term clusters is an improvement (better silicon efficiency, and faster speed) over the fixed variable distribution PAL devices, the lack of uniformity of greater than four product terms and the limited number of output pins that can receive the maximum number of product terms lead to the problems described above.
In the next generation of programmable logic devices as disclosed in the copending and commonly assigned U.S. patent application, Ser. No. 07/924,685, entitled xe2x80x9cArchitecture Of A Multiple Array High Density Programmable Logic Device With A Plurality Of Programmable Switch Matricesxe2x80x9d, of Om P. Agrawal et al., filed on Aug. 3, 1992, which is incorporated herein by reference in its entirety, additional logic allocation resources were provided and the number of product terms deepened. Specifically, the output terminal of each router element in logic allocator 315 still was connected to four product-term clusters, but the number of product terms per cluster was increased and an output switch matrix 340 was added to increase the product-term routing flexibility to the I/O pins.
The operation of logic allocator 315 is illustrated in FIG. 3. Boxes L0 through L15 on the left-hand side of the figure, each of which contains the numeral xe2x80x9c5xe2x80x9d, represent five product-term clusters in PAL structure 310. On the right-hand side of FIG. 3 are boxes BC0 through BC15 where each box represents logic that couples an output signal of logic allocator 315 to output switch matrix 340. The number within boxes BC0 to BC15 is the maximum number of product terms that logic allocator 315 can route to that logic macrocell. Each line within logic allocator 315 represents a router element, and the numbers on a line within logic allocator 315 represent the product-term clusters, as numbered on the left-hand side of the figure, that can be steered to a logic macrocell by the router element. Thus, in this PLD, the output terminal of the router element also is programmably connectable to a maximum of four product-term clusters.
Again, no product-term resources were permanently allocated to a specific logic macrocell or to a specific I/O pin by logic allocator 315. In another embodiment(not shown), PAL structure 310 includes an additional fifteen product terms over those described above. These additional product terms provide full wrap-around emulation so that in this embodiment, the logic allocator provides up to twenty product terms to each logic macrocell.
In FIG. 3, output switch matrix bank 340 programmably steers the output signal from a particular logic macrocell to a particular I/O pin. This capability enhances the symmetry of a programmable logic block at the I/O pins without adding additional product terms.
Specifically, logic allocator 315, as shown in FIG. 3, does not support complete wrap-around. In prior art PLDs with a logic allocator that did not support complete wrap-around as in FIG. 1, some I/O pins had access to a smaller number of product terms than other I/O pins. Thus, as shown above, some I/O pins had a programmably fixed and different range of logic capability than the programmably fixed range of logic capability for other I/O pins.
However, output switch matrix bank 340 steers signals from logic macrocells BC0 to BC15 to I/O pins so that a group of I/O pins may be configured to have the same logic capability independent of the relationship of the I/O pin to a logic macrocell that has a lesser logic capability. Hence, to the user application, the PLD appears to have better symmetry than the prior art PLDs because no I/O pin has a fixed logic capability.
Output switch matrix 340 partially compensates for non-uniform logic allocator 315 and aids in maintaining pin-out with logic design changes. Specifically, the output signal from a particular macrocell could be routed to a subset of the I/O pins of the logic block and so it was easier to route a particular macrocell output signal to a particular pin. This significantly assisted in maintaining the pin-out with logic designs by improving the amount of logic associated with an I/O pin.
However, while this eased the design change problem, the basic non-uniform product-term distribution remained. Output switch matrix 340 did not improve the logic associated with the macrocell. The amount of logic associated with the macrocell is limited by the flexibility of logic allocator 315. The maximum amount of logic associated with a macrocell determines the feedback capability. If a macrocell is allowed to have only up to twenty product terms, the maximum amount of feedback from the macrocell is also restricted to be twenty product terms. For complex state machines, if a macrocell needs more product terms than the twenty product terms, logic has to be feedback via the centralized switch matrix which results in increased delay.
Output switch matrix 340 also introduces some additional signal time delay. This time delay is on top of the time delay associated with logic allocator 315. Thus, a signal traversing from pin to pin incurs two delays, a logic allocator time delay plus the output switch matrix time delay.
While the logic allocators in FIGS. 1 and 3 are a great improvement over the fixed, variable distribution PLDs, a new logic allocation method and structure are needed that provides logic efficiency with a minimum number of fixed resources for very high-density PLDs. Preferably, the new structure would minimize the speed delays and would not require too much silicon area.
A programmable optimized-distribution logic allocator of this invention overcomes the shortcomings of the prior art logic allocators and enhances the speed, silicon utilization, logic efficiency, logic utilization, and scalability of-very high-density complex PLDs that uses the new logic allocator. The programmable optimized-distribution logic allocator provides programmable access to the same optimized-distribution of product terms to each I/O pin of the PLD and to each macrocell in the PLD. Thus, the product-term feedback from an I/O pin and the associated macrocell are the same. However, no product terms are permanently connected to either a particular macrocell or a particular I/O pin.
According to the principles of this invention, each logic macrocell in the programmable logic block has programmable access to at least twenty product terms, i.e., the product-term allocation for the twenty product terms is uniform, symmetric, and variable. In one embodiment, the number of product terms that can be programmably steered by the programmable optimized-distribution logic allocator, i.e, the number of product terms available, to a logic macrocell and consequently an I/O pin ranges from zero to one-half of the total number of product terms dedicated to logic in a programmable logic block for a set of the I/O pins.
The uniform and variable logic product-term cluster distribution of the programmable optimized-distribution logic allocator with a uniform twenty product terms programmably available to each macrocell provides several major benefits. First, the need for xe2x80x9cwrap-aroundxe2x80x9d at the boundaries of the programmable logic array for better product-term allocation has been obviated. Second, the need for an output switch matrix between the logic macrocells and the I/O cells also has been obviated. Third, up to thirty-two product terms are available without feedback, i.e., the a greater logic depth is available in a single pass through the PLD. The programmable optimized-distribution logic allocator achieves the flexibility of optimal routability of logic product-term clusters to I/O pins which allows retaining a prior pin-out while changing a logic design. In addition, the twenty logic product terms can be routed to a particular logic macrocell without any additional speed penalty. This number of product terms is typically sufficient to allow complete shuffling of the logic mapped on the PLD with the ability to retain prior pin-outs and removes any dependencies of product-term clusters between adjacent macrocells.
In one application, the programmable optimized-distribution logic allocator includes a multiplicity of router elements where each router element steers a sum of a selected number of sum-of-product terms from a PAL structure, i.e, a selected number of logic product-term clusters, to a programmably selected logic macrocell. Specifically, the programmable optimized-distribution logic allocator has a plurality of input lines, a plurality of output lines and a plurality of programmable router elements. Each programmable router element has an output terminal connected to an output line in the plurality of logic allocator output lines. Also, each programmable router element output terminal is programmably couplable to and decouplable from at least five of the programmable logic allocator input lines so that each output line has access to all input signals on at least five input lines in the plurality of logic allocator input lines. Upon coupling a logic allocator input line to a router element output terminal, the input line is decoupled from all other router element output terminals in the logic allocator.
In this embodiment, each programmable router element includes a programmable demultiplexer having an input terminal connected to an input line in the plurality of logic allocator input lines, and a plurality of output terminals. The input terminal is programmably connectable to and disconnectable from the plurality of output terminals, and upon programmably connecting the input terminal to one of the plurality of output terminals, the input terminal is disconnected from all other output terminals in the plurality of output terminals
The programmable router element also includes a logic gate having a plurality of input terminals, and an output terminal. Each logic gate input terminal is connected to an output terminal of a different programmable demultiplexer.
In one embodiment, the programmable router element further includes an exclusive-OR gate having an input terminal connected to the output terminal of the logic gate, and an output terminal connected to one of the plurality of logic allocator output lines.
Thus, according to the principles of this invention, a method for distributing product terms from a programmable array in a very high-density PLD to logic in the very high-density PLD includes: (i) coupling each product-term cluster in a plurality of product-term clusters to a different input line of a programmable logic allocator; and (ii) configuring the logic allocator, i.e., programmably coupling the input lines to the output lines of the logic allocator, so that each output line of the logic allocator has programmable access to a first predetermined number of product-term clusters in the plurality of product-term clusters where the first predetermined number of product-term clusters includes at least twenty product terms. The input lines are programmably coupled to the output lines so that upon programmably coupling a product-term cluster to an output line of the logic allocator, the coupled product-term cluster is decoupled from all remaining output lines of the logic allocator.
Further, configuration of the logic allocator also includes configuring the logic allocator so that a set of the output lines of the logic allocator has programmable access to both the first predetermined number of product-term clusters and a second predetermined number of product-term clusters in the plurality of product-term clusters. The sum of the product terms in the first and second predetermined numbers of product-term clusters is in the range of from twenty product terms to one-half of the product terms in the plurality of product-term clusters. In one embodiment, one-half of the product terms in the plurality of product-term clusters is thirty-two product terms.
The programmable optimized-distribution logic allocator includes a plurality of N input lines where N is an integer, a plurality of N output lines where N is an integer, and a multiplicity of programmable router elements. The multiplicity of programmable router elements includes a first plurality of programmable router elements where each router element in the first plurality of programmable router elements is connected to a different output line in the plurality of N output lines. Also, each output terminal of each router element in the first plurality of programmable router elements is programmably couplable to and decouplable from at least M input lines in the plurality of N input lines so that each output line connected to one of the router elements in the first plurality of programmable router elements has programmable access to all input signals on M input lines in the plurality of N input lines where M is an integer.
The multiplicity of programmable router elements includes also a second plurality of programmable router elements. Each router element in the second plurality of programmable router elements is connected to a different output line in the plurality of N output lines. The output lines connected to the router elements in the second plurality are also different from the output lines connected to the router elements in the first plurality. The output terminal of each router element in the second plurality of programmable router elements is programmably connectable to and disconnectable from at least (Mxe2x88x92n) logic allocator input lines so that each output terminal of the router elements in the second plurality of programmable router elements has programmable access to all input signals on (Mxe2x88x92n) input lines in the plurality of N input lines where the n is an integer in a range from 1 to 3 and M is selected so that when n is three, (Mxe2x88x92n) is at least five. In one embodiment, N is sixteen and M is eight.
Thus, the programmable optimized-distribution logic allocator has a plurality of N input lines where N is an integer, a plurality of N output lines, and a plurality of programmable router elements with each programmable router element having an output terminal connected to an output line in said plurality of N output lines. Each programmable router element output terminal is programmably couplable to and decouplable from at least five programmable logic allocator input lines so that each logic allocator output line has programmable access to all input signals on a minimum of five input lines in said plurality of N input lines.